What are known as single-transistor cells are used in dynamic random access memories (DRAMs). These cells comprise a storage capacitor and a select transistor (MOSFET), which connects the storage electrode to the bit line. The storage capacitor may be designed as a trench capacitor or as a stacked capacitor.
To drive the select transistor, a metalically conductive gate electrode stack is placed onto the gate oxide. Typical gate electrode stacks are stacks comprising doped polysilicon and, above it, a tungsten silicide (WSix) or a tungsten nitride/tungsten sandwich.
Patterning of a gate electrode stack of this type, for example by a plasma etch, by means of an additional silicon nitride capping layer on the upper tungsten-containing electrode layer, together with corresponding gate contacts, provides the metallic connection lines.
The patterned gate electrode stacks are usually subjected to a thermal aftertreatment in such a manner that simultaneously the uncovered side walls are partially oxidized and the resistance in the metal is minimized by targeted phase transformation or grain growth. The thin film of oxide which is thereby formed on the side walls of the polysilicon improves the leakage current characteristics of the transistors and acts as a spacer for the subsequent LDD (lightly doped drain) implantation. The latter sets the transistor parameters over the defined gate length. The metallic phase transformation at typical temperatures of 1000 to 1080° C. leads to a reduction in the resistance and is associated with strong grain growth in the gate metal.
In the process as currently used, the conditioning takes place at between 1000 and 1080° C. after the patterning of the gate electrode stack immediately before the LDD implantation. This known process leads to the following problems.
When tungsten silicide (WSix) is used, grains grow out laterally beyond the side faces of the gate electrode stack, which have been etched smooth, forming a partial alloy with the polysilicon below. These lateral projections, in particular in future technology generations with a feature size of <170 nm, may lead to short circuits with adjacent metal contacts, since they may be etched open during the contact etch.
DRAM technologies with transistor gate lengths of less than 110 nm require modified cell architectures with lower resistances and connections which are free of short circuits.
The use of tungsten without Si alloy with a tungsten nitride diffusion barrier with respect to the polysilicon below fulfils the requirements relating to the resistance. However, tungsten as gate metal is not suitable for current processes, since during the subsequent processing involved in thermal and oxidation processes, it escapes as a gas or sublimes as WOx and is precipitated at the chamber inner walls, making it impossible to control the side wall oxidation.